`timescale 1us/1us
module fsm2_2_tb ();
   reg clk;
   reg reset;
   wire led;

   fsm2_2 fsm2_2(
    .clk(clk),
    .reset(reset),
    .led(led)
   ); 

    defparam fsm2_2.contmax=20;

   initial begin
            clk<=0;
            reset<=0;
    #10     reset<=1;
    #9000   $stop;
   end

   always #1 clk<=~clk;
endmodule

